vhdl example code parallel to serial converter

Refer following as well as links mentioned on left side panel for useful VHDL codes.

Information to be converted to analog format for transmission.ĭAC FPGA VHDL/VERILOG code for the same can be easily written. In DAC FPGA interface, SYNC is pulled HIGH and then 16 bits are being written.įirst 2 bits are zeroes, next 2 bits are configuration bits and rest 12 bits are actual ADC FPGA VHDL/VERILOG code for the same can be easily written. The 12 bit represents voltage acquired by the ADC. In ADC FPGA interface, CS is pulled low and then four zeroes are being transmitted which isįollowed by 12 bits. Both ADC and DAC are 12 bit analog to digital converter andġ2 bit digital to analog converters respectively. The figure-3 depicts ADC and DAC serial data interface timing diagram obtained fromĭatasheets of the ADC/DAC. Imag_adc_to_phy<= imag_in_from_ADC(11)& imag_in_from_ADC(11)& imag_in_from_ADC(11)& imag_in_from_ADC(11)& imag_in_from_ADC Įnd beh ADC DAC Serial data interfacing with FPGA Imag_adc_to_phy : out std_logic_vector(15 downto 0) -receiver side o/pĮlsif CLK_SAMP='1' and CLK_SAMP'event then The following circuit is a four-bit Serial in parallel out shift register constructed by D flip-flops. Real_adc_to_phy : out std_logic_vector(15 downto 0) -receiver side 0/p For Serial in parallel out shift registers, all data bits appear on the parallel outputs following the data bits enters sequentially through each flipflop. Imag_in_from_ADC : in std_logic_vector(11 downto 0) -receiver side i/p parallel to serial converter here is a code, this will only work when the input en is changed along with the posedge of clock. MUX:ENTITY WORK.Real_in_from_ADC : in std_logic_vector(11 downto 0) -receiver side i/p STRUCTURAL STYLE OF MODELLING IS USED TO BIND THE INDIVIDUAL COMPONENTSĬOUNTER:ENTITY WORK.COUNTER_123 PORT MAP(CLK,QOUT_1)

SIGNAL QOUT_1:STD_LOGIC_VECTOR(2 DOWNTO 0)

PORT(DIN_1:IN STD_LOGIC_VECTOR(7 DOWNTO 0) CLK:IN STD_LOGIC DOUT_1:OUT STD_LOGIC) Figure 2 Serial to Parallel conversion example. VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0):='000' The parallel output to the module will be available every N clock cycle since N clock cycles are needed to load the shift register that provided the parallel output as in Figure2. SIGNAL TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0):='000' PORT(CLOCK:IN STD_LOGIC QOUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0)) WHEN'000'=>DOUTDOUTDOUTDOUTDOUTDOUTDOUTDOUT PORT(DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0) SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0) DOUT:OUT STD_LOGIC)

It consists of 3 parts:1)Code for 8:1 multiplexer, 2)Code for 3 bit counter, and 3)Structural binding of (1) and (2).The code is shown below.Remember,the port name of last entity is shown in the logical diagram. Working:The parallel data is applied at the input of multiplexer.The select input of the multiplexer is connected to the output of the 3 bit counter.As the count increases the select input of the multiplexer changes,and hence each of the parallel inputs are connected to single output line of multiplexer.Thus parallel to serial conversion takes place.Here I used a simple behavioral code for the counter.In stead of this code ,you can use your own design. Simply a parallel to serial converter consists ofĪ simplified logic diagram of the circuit is shown here. This circuit is very much useful in designing a microprocessors and microcontrollers.In processor,data is in parallel format.But sometimes we need data as bit by bit(Example :To transfer data from processor through serial bus).So it is very useful. This is the model of a parallel to serial converter.

Vhdl example code parallel to serial converter